Total 18 job vacancies by Cadence

We are looking for an Accounts cum Admin Intern to assist our team in various administrative and accounting tasks. The ideal candidate will be detail-oriented, organized, and eager to learn. This internship provides an excellent opportunity to gain hands-on experience in both accounting and administrative functions within a fast-paced and supportive environment.

Responsibilities:

• Prepare documents in both English and Chinese.
• Assist with accounting tasks, including data entry, invoicing, and reconciliations.
• Answer phone calls and direct inquiries to the appropriate team members.
• Respond to emails in a professional and timely manner.
• Assist in purchasing office supplies.
• Utilize Microsoft Office Suite for various administrative tasks.

Requirements:

• Proficiency in both English and Chinese (written and verbal).
• Basic understanding of accounting principles and practices.
• Strong communication and interpersonal skills.
• Detail-oriented with excellent organizational abilities.
• Ability to multitask and prioritize tasks effectively.
• Proficient in Microsoft Office Suite (Word, Excel, Outlook).

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:
- Internship working on Pegasus products related projects
- Projects for interns are under internal discussion and will be determined by July

Position Requirements:
- Computer science
- Good C++/python programming skill

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Working with the Cadence Tensilica XPG group to

• Develop a Java/Groovy program that transforms configurable processor descriptions from an internal model into alternate representations using templates with embedded language constructs.
• And also build a test harness to verify that the resulting transformations are correct.

Requirements:

• Currently enrolled in BS or MS in CS, CE, or equivalent.
• Core java data structures and algorithms
• Software engineering practices and source control systems
• Automation techniques for broad testing of transformation
• Ideally also 
  • server based web page generation for transformation output
  • SQL database knowledge for recording / reporting test data

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:

The intern software engineering position will support and help on ML-based mapping file generation.

Position Requirements:
- Computer science or EE related
- Good Python programming skill with AI/ML background

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Functional Verification Engineer for DDR Memory Controller and Phy IP development team.
• The role would include functional verification of the DDR Memory Controller and Phy IP solution of Cadence.
• The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
• The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.

Position Requirements:

• BS/MS - Electrical/Electronics/VLSI
• Strong background on Digital design and functional verification fundamentals
• Exposure/expertise in System Verilog and UVM based functional verification environment development is required.
• Scripting knowledge will be a plus.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. Fortune magazine has named Cadence one of the 100 Best Companies to Work For for nine years in a row.

About the Global Strategic Sourcing (GSS) organization: We are about People. Partnership. Performance. We provide strategic value in Cadence’s procurement process that includes spend visibility, sourcing, contract management, operations, and supplier management. Procurement proactively delivers a simplified and efficient solution that improves our customers' experience while ensuring compliance/risk mitigation and identifying cost savings opportunities.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. Fortune magazine has named Cadence one of the 100 Best Companies to Work For for nine years in a row.

About the Global Strategic Sourcing (GSS) organization: We are about People. Partnership. Performance. We provide strategic value in Cadence’s procurement process that includes spend visibility, sourcing, contract management, operations, and supplier management. Procurement proactively delivers a simplified and efficient solution that improves our customers' experience while ensuring compliance/risk mitigation and identifying cost savings opportunities.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the team:
Our team deliver many high-performance products based on the industry’s advanced technology with high frequencies up to 6400MHz. Our product processes include TSMC 3nm/5nm/7nm/12nm and Samsung 4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Focus on high speed digital DDR and HBM IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.

实习 - 数字后端工程师 (工作地点：上海)

职位描述：
(1)芯片物理设计, 后端布局布线，STA，物理验证等。
(2)团队合作，负责电路后端设计及交付，设计质量和进度控制

职位需求：
(1)微电子,电子工程硕士以上学历
(2)较强的问题分析以及团队合作能力
(3)较强的中英文口语沟通及写作能力
(4)熟悉数字后端工具
(5)积极主动, 有责任心

**每周可以工作至少3天，实习期6-8个月

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

You will be a member of the team responsible for optimizing Neural Networks for Tensilica DSPs and hardware accelerators. You will gain familiarity with the Tensilica NeuroWeave Neural Network Compiler and use your knowledge to optimize Neural Network applications for Tensilica processors/accelerators.

Required Skills: 

* Understanding of neural network architectures, applications and accuracy evaluation

* Familiarity with neural network optimization techniques such as quantization (post training and qantization aware)

* Expertise in NN frameworks such as Tensorflow and Pytorch

* Good programming skills in programming languages such as C++ and Python

* The ideal candidate would be working towards a Master’s or PhD in Computer Science/Engineering or Electrical Engineering or related field

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description :

The Allegro Applications Team is looking for an intern to join them this summer. As a member of this team, you’ll gain hands on experience working with enterprise level software and solving real world problems.  This team has a wide range of responsibilities, including application GUIs, API integration, enhancing/maintaining application infrastructure, and much more.  You’ll have the opportunity to work in one or more of these areas, all while learning about the software development process and what it looks like to be a software developer.

Key Responsibilities:

• The person will be part of team responsible for developing analytics applications on Cadence JEDAI platform. Knowledge in areas of circuit simulation, ML, data processing will be useful.

Requirements:

• Currently enrolled in Bachelors or Masters program majoring in Computer Science (or related field) and graduating in Winter 2024 or Spring/Summer 2025.
• Skills and experience in C++ and Python development are necessary.
• Functional knowledge of NodeJS and Apache Airflow development would be desired
• Excellent verbal and written communication skills.
• Strong curiosity and a passion for learning.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a candidate to join the Silicon Package Board (SPB) team as an intern focused on Advanced Packaging Design. If you like to architect and develop solutions for challenging problems in a fast and innovative paced environment, using state of the art technology this is a great opportunity.

This position is located in Belo Horizonte-MG.

Job Description:

 The Candidate will be trained on the Cadence Integrated Circuit (IC) Package Design tool set, working with state-of-the-art complex IC packaging of electronics using highly integrated IC package co-design and multi-die chiplet methodologies. Understand of competitive technologies is a plus. Ability to understand schematic, layout, interposers, integrated components.  

Key responsibilities in this position are to:

• Helping customers to adopt and proliferate our packaging solutions
• Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations
• Supporting technical evaluations and benchmarks
• Help R&D and product engineers develop competitive and creative technical solutions

The ideal candidate will be self-motivated, have strong problem-solving skills and able to work independently with minimal supervision.

Minimum Requirements

• Enrolled on Electrical, Electronics, System Engineering, computer science or related areas on progress
• Excellent written and verbal communication skills
• Interest in learning new technologies
• Open to continued personal development to meet the evolving demands of the EDA industry
• One to two years to graduate

Nice to have skills

• Previous experience with Package or PCB Design
• Knowledge of EDA industry, Signal and Power Integrity
• Electromagnetics, and RF related to IC Package and PCB Design are desirable
• Ability to present and clearly articulate
• Knowledge of scripting programming languages such as Tcl, Perl, Python, bash, csh

Additional Job Details:

• Internship term: 20 hours/week
• Location: Av. do Contorno, 5800, Savassi - Belo Horizonte

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated intern of the Hardware System Verification in Belo Horizonte. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.

Position Description:

The activities will include design, development, testing and maintenance of features in tools related to hardware emulation. You will be working as part of a dynamic, challenge-oriented group as well as interacting with other developers and product experts around the world.

The candidate should have:

• Education: bachelor's degree in progress ( One or two years to graduate);.
• Interest in Python, Linux OS, Verilog/VHDL
• Basic knowledge with git, pforce,
• Eager to learn scripting languages (bash and tcl); advanced algorithms and data structures;
• Verbal and written communication in English;
• Willingness to learn and tackle challenges;
• Interpersonal skills;
• familiarity with digital logic design

Nice to have:

• Verilog/System Verilog/VHDL knowledge;
• GO language knowledge is a big plus;
• Agile scrum knowledge;

Additional Job Details:

• Employment category: Internship
• Employment term: 30 hours/week
• Location: Avenida do Contorno 5800, Savassi, Belo Horizonte

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.

For more information and others opportunities, access https://cadence.wd1.myworkdayjobs.com/External_Careers/2/refreshFacet/318c8bb6f553100021d223d9780d30be

Make your mark.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Silicon Solutions.

Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great SSG Team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of two roles:
(a) Perform as a member of the Logic Design Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for the RTL implementation of high performance memory system and interconnect components. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for verification of high performance memory system and interconnect components. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Position Requirements:
• Currently enrolled as MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Tensilica Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 Billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica Processor Team is hiring graduates to join our R&D teams in San Jose and Austin. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of the three roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

(c) Perform as a member of the Functional Safety Team for Xtensa processors. Responsible for Functional Safety features verification of microprocessor cores leading to certification for deployment of the cores in Automotive or Industrial systems. Assist with developing fault injection, writing functional assembly diagnostics, debugging failures, and analyzing coverage information. Work closely with various RTL Design teams.

Position Requirements:
• MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.