• Provides assistance in matters involving tribal organic documents, such as constitutions, ordinances, resolutions, election procedures, Section 17 federal corporate charters, and amendments to those organic documents, Secretarial Elections, intra-tribal disputes, and implementation of DOI and BIA policies.
• Provide consultation and technical assistance to Tribes regarding their governmental and corporate functions to ensure the Tribes maintain stable governments.
• Conducts records management projects.
• Maintains and manages confidentiality of records and files.
• Prepares training material, such as enrollment, developing, amending, or revising constitutions, drafting of tribal ordinances, conducting tribal elections, and Secretarial Elections.
• Reviews tribal budgets, plans of distribution, tribal constitutions and other tribal organizational documents to see that all Federal statutes, regulations, procedures and tribal constitutional requirements are adhered too.
• Maintain current Tribal information regarding statistics, governmental information, elections, organic documents, and similar Tribal resources.

As an Architect (Historical), GS-0808-11, with the National Park Service (NPS), your duties will include, but are not limited to:

• Participates in National Historic Preservation Act Section 106 consultation and compliance activities as they relate to historic structures.
• Performs architectural duties associated with review, design, treatment, and monitoring of historic and prehistoric structures.
• Collaborates on interdisciplinary teams at the park level to promote cultural resource and historic preservation stewardship goals and objectives, including review and preparation of NRHP nominations.
• Provides technical assistance and subject matter expertise as it relates to historic structures and districts.
• Identifies research needs and suitable research designs and conducts or oversees various levels of documentary research and field investigations.
• Conducts research involving historical documents, photographs, plans, drawings, and related items to develop knowledge of and data about specific historic and prehistoric structures, such as period designs.
• Negotiates cooperative and interagency agreements and other cooperative instruments needed to effectively carry out resource stewardship goals.

• You will coordinate and assign workload responsibilities to staff to prepare plans, reports, presentations or other documents that define, evaluate and/or recommend alternatives for customer, leadership or management review and action.
• You will plan work to be accomplished by subordinates, advise, counsel, or instruct employees on both work and administrative matters, hear and resolve complaints from employees.
• You will provide day to day oversight, planning and prioritization in managing the construction, repair and maintenance requirements of the installation through management of the Maintenance Execution Plan (MEP).
• You will provide day to day oversight, planning and prioritization in managing the construction, repair and maintenance requirements of the installation through management of the Maintenance Execution Plan (MEP).

• Responsible for the administration, development, execution, and evaluation of the entire Human Services Branch.
• Maintain the administration and provide case management of supervised Individual Indian Money (IIM) accounts for minors and adults.
• Provides professional level direction for family centered casework to assist in adjustments of family members toward one another, and in their relationship outside the home.
• Prepares annual program budgets, revising them as appropriate in order to conform to program activities, needs, and budgetary constraints.
• Maintains case records reflecting decisions on applications and narration of services provided.
• Responsible for coordination and consultation with agencies at tribal, local, county, state, and national level for purpose of developing and provision of social services to the Agency.
• Provide program management and technical advisement regarding diverse Bureau human services programs pertaining to Indian Child Welfare, Child and Family Services and Child Protection matters.

This role is the ideal next career step for you if:

• You want to play a key role serving as head of a Patent Examining Art Unit under the general administrative direction of the Group Director;
• You have comprehensive knowledge in interpretation of legal precedents for making a wide variety of decisions involving the subject matter unique to the Technology Center;
• You aspire to lead a diverse and inclusive team exercising the full range of supervisory and managerial duties associated with the direction of work in the art unit, developing and training employees, reviewing and evaluating the work and performance of subordinates.

If selected for a Regional Office SPE position, the incumbent will service as part of the regional office management team which includes participating in formulating, developing, and implementing policies to carry out the goals and objectives of the regional office and the USPTO.

The physical worksite for this position is located in Alexandria VA, Dallas TX, Detroit MI, San Jose CA, or Denver CO.

Applicants should familiarize themselves and must be able to comply with the relevant conflict of interest laws and standards of ethical conduct for employees of the executive branch regarding possible conflicts of interest in connection with their potential area of examination as seen here: https://www.commerce.gov/ogc/about-ogc/bureaus-and-offices/office-assistant-general-counsel-ethics-law-and-programs-office/ethics-rules

Attorney-applicants must also be able to comply with the relevant rules of professional conduct regarding any possible professional responsibility conflicts in connection with their applications. In particular, please notify the USPTO Office of Enrollment and Discipline at OED@uspto.gov if you currently represent clients before the USPTO and/or you have a family member who is representing clients or adjudicating matters in which this Office is involved so that we can evaluate any potential conflict of interest or disqualification issue that may need to be addressed under those circumstances.

You may be required to file a confidential financial disclosure report, OGE 450, annually.

• As an Engineering Technical Lead (TL) will manage the coordination and accomplishment of the planning, scoping, development, budget development, and contract oversight.
• Projects include flood risk management, coastal protection, ecosystem restoration, dam and levee safety projects, and the deepening and improvement of ship navigation channels for larger vessels.
• Solves, advises, or evaluates complex design management issues which involve difficult or unusual planning, scheduling, negotiation, coordination, communications, and contracting during design, acquisition, and construction phases.
• Engineering disciplines including architecture; civil engineering; geotechnical engineering; coastal, hydraulic and hydrologic engineering; mechanical engineering; electrical engineering; structural engineering; and environmental engineering.
• Will have responsibilities such as funds control; resource planning; contract negotiation; contract oversight; and project scheduling.
• Works closely with the Project Manager (PM) during all phase of the design, acquisition, and works closely with the Resident Engineer during the construction phase.

• Direct, coordinate, and oversee the planning and execution of a wide variety of administrative activities in the following areas: budget and finance, contracting, property, space, and supply, human resources, purchase and procurement, federal records, federal travel and timekeeping/payroll.
• Perform budgetary tasks and oversee financial management matters.
• Oversee property management and procure needed equipment, materials, supplies and services.
• Provides direction and implementing instructions for all Agency associated actions in conjunction with position management, recruitment, training, performance appraisals, grievance procedures, employee recognition program, employee orientations

As a professional historical landscape architect, you specialize in the identification, documentation, planning and preservation of cultural landscapes and other associated properties. Duties include:

• Perform landscape architectural duties associated with review, design, treatment, and monitoring of historic and prehistoric cultural landscapes.
• Participate in National Historic Preservation Act Section 106 consultation and compliance activities as they relate to cultural landscapes and historic districts.
• Collaborate on interdisciplinary teams at the park level to promote cultural resource and historic preservation stewardship goals and objectives; including review and preparation of NRHP nominations.
• Provide technical assistance and subject matter expertise as it relates to cultural landscapes and districts.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, Power Characterization.

Lead technical campaigns and strategies in the Frontend digital implementation space. 

Aggressively push Power, Performance, and Area (PPA)

Deliver technical presentations and lead discussions internally and with customers. 

Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.

Support execution on critical customer flagship product tape outs.

Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.

Job Requirements

Minimum

MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 8+ years industry experience.

Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.

Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking, Low Power, Power characterization.

Expert in RTL Synthesis and ability to rewrite RTL to accomplish improved PPA.

Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.

Experience with advanced technology nodes including Sub 5nm and below.

Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)

Strong customer-facing communication and problem-solving skills

Strong personal drive for continuous learning and expanding professional skillsets.

Strong verbal, written, and customer communication skills.

Preferred

Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite

Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.

#LI-MA1

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Title

Lead Applications Engineer, Design IP

San Jose/Hybrid

Job Description

The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems. We offer amazing opportunities to grow, no matter where you are in your career.

We are growing our Serdes Applications team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged?  Join the High-Performance Culture at Cadence.

As a Lead Applications Engineer, you will use your knowledge of different high-speed interface standards such as PCIe, CXL, Ethernet and USB to architect interface solutions for customers using Cadence Serdes IP and showcase the performance of the IP.  This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions to them using our Serdes IP portfolio.  Our serial interface PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices.

Responsibilities include:

·       Technical presales and configuration of High-Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers

·       Present Cadence’s IP portfolio and capabilities to prospective customers

·       Serve as a product expert in digital controller and PHY IPs and protocols

·       Work closely with IP Sales staff, marketing and R&D teams to win opportunities

·       Demonstrating IP Performance at industry events and to prospective customers

·       Provide quick-turn product specific technical support to customers, field teams, architects and designers

·       Write application notes and articles for internal and/or external publication

·       Travel to customer sites may be required occasionally

Qualifications:

·       BS in EE, CE or related equivalent with 6+ years of relevant work experience or MS in EE, CE or equivalent with 4+ years of relevant work experience

·       Knowledge of one or more high speed interface protocols – PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G

·       Strong knowledge of PHY and/or controllers for one or more high speed interface protocols

·       Individual leadership and initiative to manage pre-sales accounts

·       Excellent presentation skills and verbal/written communication skills is a must

Nice to have:

·       Lab validation and demo setup skills

·       Experience on high-speed interface controller and/or PHY verification

·       Knowledge of AXI and PIPE interface protocols

·       Working knowledge of high-speed interface PHY

The annual salary range for California is $98,000 to $182,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Title

Senior Applications Engineer, SerDes Design IP

San Jose, CA/Hybrid

Job Description

The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems. We offer amazing opportunities to grow, no matter where you are in your career.

We are growing our Serdes Applications team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged?  Join the High-Performance Culture at Cadence.

As a Senior Applications Engineer, you will use your knowledge of different high-speed interface standards such as PCIe, CXL, Ethernet and USB to provide technical pre-sales support to win design IP business and showcase the performance of the IP through demos at industry events. This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions to them using our Serdes IP portfolio.  As you grow into more senior roles, you will use your knowledge of different high-speed interface standards to architect solutions for customers using Cadence IPs. Our serial interface PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices. Cadence offers great benefits and has a friendly hybrid work policy with three days in office.

Responsibilities include:

·       Technical pre-sales of High-Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers

·       Present Cadence’s IP portfolio and capabilities to prospective customers

·       Work closely with IP Sales staff, marketing and R&D teams to win opportunities

·       Provide quick-turn product specific technical support to customers, field teams, architects and designers

·       Write application notes and articles for internal and/or external publication

·       Travel to customer sites may be required occasionally

Qualifications:

·       BS in EE, CE or related equivalent with 2+ years of relevant work experience or MS in EE, CE

·       Individual leadership and initiative to manage pre-sales accounts and sell IP

·       Excellent presentation skills and verbal/written communication skills is a must

Nice to have:

·       Experience on high-speed interface controller and/or PHY design/verification

·       Working knowledge of high-speed interface PHY

·       Knowledge of one or more high speed interface protocols – PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G

·       Lab validation or demo setup experience

The annual salary range for California is $80,500 to $149,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Silicon Solutions.

Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great SSG Team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of two roles:
(a) Perform as a member of the Logic Design Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for the RTL implementation of high performance memory system and interconnect components. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team on a Digital Design project such as an L2 Cache or a Network on Chip project. Responsible for verification of high performance memory system and interconnect components. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Position Requirements:
• Currently enrolled as MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

Business Unit:

Company Details:

Job Details:

• An expert level understanding of network infrastructure design and best practice principles including routing and switching concepts and technologies, advanced IP addressing, dynamic routing protocols. MPLS, Secure and resilient routing solutions, Unified communications, Load balancing and traffic management, Quality of Service (QOS), Wireless and Mobile communications.
• Highly advanced troubleshooting and problem diagnosis skills developed from proven experience
• Subject Matter Expert responsible for mentoring our global staff including skills evaluation, change implementation reviews and partnership with our global network manager
• An in-depth understanding of end-to-end secure network concepts, technologies and
• protocols including Access control, Next generation, Web application and Stateful firewalls technologies, Intrusion prevention, Encryption (IPSEC, SSL, PKI), Security event information management systems, Proxy services.
• Responsible for designing solutions, aligned with customer requirements for projects initiated by supported lines of business in coordination with other technical departments
• Works with a wide range of engineering resources as needed, ensuring that end-to-end network design is completed
• Prepares design specifications, analyses and recommendations based on customer requirements. Including networking, cloud, on-premise solutions. 
• Researches system designs and enhancement solutions.
• Partners with project team to complete technical design documents
• Partners with PM to document implementation tasks for the project
• Responsible for ensuring that the designed solution addresses all business and systems (functional/non-functional) requirements
• Maintains liaison with customer, subcontractor and vendor representatives.
• Evaluates vendor capabilities to provide required products or services.
• Conducts in-house design reviews and technical meetings.
• Makes presentations before management and customers.
• Assumes additional technical and non-technical responsibilities as needed include proof-of-concepts and implementing solution designs.
• Hybrid position on-site at San Diego headquarters or West Coast USA.
• Travel domestic and international up to 25% as needed.

Minimum Job Requirements:

• Education: Bachelor’s degree in Computer Science, Information Systems, Electronic Engineering or other related technical discipline, and/or the combined equivalent of education and experience.
• Ten years' experience, including network design/development/implementation, providing technical direction and leadership to team members.
• Competent use of Microsoft Office applications, including Word, Excel, Project, Visio, PowerPoint..
• Excellent written and verbal communication skills Able to positively interact with customers, subcontractors and vendors. 
• Must be able to solve complex and difficult system problems.
• Some travel may be required.
• Able to work flexible hours as required.
• Ability to manage simultaneous projects in multiple locations across the United States and internationally.
• Self-driven and resourceful to achieve goals independently as well as work well in groups.
• Experience developing Networking Solutions as a lead engineer, architect or manager.  
• Cloud-based networking experience in public and private cloud environments (preferred Azure).
• Experience network engineering and administration to include L2, L3, and L7 switches, preferably Cisco. 7+ years’ managing vendor relationships and working with professional engagements.

The description provided above is not intended to be an exhaustive list of all job duties, responsibilities and requirements.  Duties, responsibilities and requirements may change over time and according to business need.

Additional Information 

(San Diego only***) Targeted full-time salary between $165,000 - 188,000 + benefits.  

***Note: Disclosure of the pay scale data as required by Labor Code Section 432.3. 

The Cubic pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law. 

Worker Type:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Tensilica Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 Billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica Processor Team is hiring graduates to join our R&D teams in San Jose and Austin. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of the three roles:
(a) Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.
(b) Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

(c) Perform as a member of the Functional Safety Team for Xtensa processors. Responsible for Functional Safety features verification of microprocessor cores leading to certification for deployment of the cores in Automotive or Industrial systems. Assist with developing fault injection, writing functional assembly diagnostics, debugging failures, and analyzing coverage information. Work closely with various RTL Design teams.

Position Requirements:
• MS/BS in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills
• Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

DSP Design Verification Engineer

Position Description

Key member of the Tensilica DSP team within Cadence, responsible for design verification of DSP based hardware products as part of families of Tensilica DSPs and hardware accelerators, targeting various application domains such as computer vision, AR/VR, audio/voice, Radar, AI or ADAS/AD.

Be part of an agile team with experts in DSP architecture, design, implementation, and HW/SW verification. Gain understanding of the DSP algorithms and mathematical functions being implemented. Architect and implement verification environments and tests to ensure that the implementation is correct, there are no functional bugs, and the performance criteria were met. Design, implement and maintain large scale regression frameworks that improve quality and project execution time.

RESPONSIBILITIES:

• Collaborate with architecture/design team to understand the algorithms and mathematical functions.
• Define and develop detailed test plans.
• Develop tests in C/C++ to create a behavioral model of the DSP functions, using fixed point or floating point arithmetic.
• Develop and maintain extensible/large scale regression flows and infrastructure, including tools for aggregating metrics and trending.
• Develop System Verilog/UVM testbenches and checkers.
• Apply formal verification methodology for verification sign off and quality.
• Develop and apply novel techniques for verifying performance of designs.

Position Requirements:

• Knowledge of DSP arithmetic functions. Domain specific knowledge in Audio, Computer Vision, AR/VR, Radar or AI desirable but not necessary.
• Knowledge of computer architecture, especially hardware micro-architecture, processor pipelines and instruction sets.
• Familiarity with hardware verification concepts such as assertions, scoreboard, and some knowledge of System Verilog.
• Strong understanding of Software development.
• Proficiency in C/C++.
• Proficiency in any scripting language (Python or Perl preferred).
• Familiarity with source code control (Git/Perforce).
• Ability to work efficiently with remote teams on different time zones
• Ability to work successfully both independently and in a team environment
• Strong problem-solving skills, flexible, adaptable and proactive 
• Strong communication skills 
• MSEE, MSCS, or MSCE or equivalent.
• MS and 3+ years of working in a design or verification role, or some internship experience if pursuing a PhD.

The annual salary range for California is $128,100 to $237,900. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.